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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9328MXL Rev. 8, 12/2006
MC9328MXL
MC9328MXL
Package Information Plastic Package Case 1304B-01 (MAPBGA-225) Ordering Information See Table 1 on page 3
1
Introduction
Contents
1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signals and Connections . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . 17 Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Pin-Out and Package Information . . . . . . . . 84 6 Product Documentation . . . . . . . . . . . . . . . . 88 Contact Information . . . . . . . . . . . . . . . Last Page
The i.MX Family of applications processors provides a leap in performance with an ARM9TM microprocessor core and highly integrated system functions. The i.MX family specifically addresses the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The MC9328MXL (i.MXL) processor features the advanced and power-efficient ARM920TTM core that operates at speeds up to 200 MHz. Integrated modules, which include a USB device, an LCD controller, and an MMC/SD host controller, support a suite of peripherals to enhance portable products seeking to provide a rich multimedia experience. It is packaged in either a 256-contact Mold Array Process-Ball Grid Array (MAPBGA) or 225-contact MAPBGA package. Figure 1 shows the functional block diagram of the i.MXL processor.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved.
Introduction
System Control JTAG/ICE Bootstrap
Power Control
CGM (PLLx2)
Standard System I/O GPIO
Connectivity MMC/SD
MC9328MXL
CPU Complex
PWM Timer 1 & 2 RTC
Memory Stick(R) Host Controller ARM9TDMITM SPI 1 and SPI 2 UART 1 UART 2 SSI/I2S I2C USB Device AIPI 2 DMAC (11 Chnl) EIM & SDRAMC Bus Control I Cache D Cache
Watchdog
Multimedia Multimedia Accelerator Video Port
AIPI 1
VMMU
Interrupt Controller
Human Interface LCD Controller
Figure 1. i.MXL Functional Block Diagram
1.1
* * * * * * * * * * * * * * * * * *
Features
ARM920TTM Microprocessor Core AHB to IP Bus Interfaces (AIPIs) External Interface Module (EIM) SDRAM Controller (SDRAMC) DPLL Clock and Power Control Module Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2) Serial Peripheral Interface (SPI) Two General-Purpose 32-bit Counters/Timers Watchdog Timer Real-Time Clock/Sampling Timer (RTC) LCD Controller (LCDC) Pulse-Width Modulation (PWM) Module Universal Serial Bus (USB) Device Multimedia Card and Secure Digital (MMC/SD) Host Controller Module Memory Stick(R) Host Controller (MSHC) Direct Memory Access Controller (DMAC) Synchronous Serial Interface and an Inter-IC Sound (SSI/I2S) Module Inter-IC (I2C) Bus Module
MC9328MXL Technical Data, Rev. 8
To support a wide variety of applications, the processor offers a robust array of features, including the following:
2
Freescale Semiconductor
Introduction
* * * * * * * *
Video Port General-Purpose I/O (GPIO) Ports Bootstrap Mode Multimedia Accelerator (MMA) Power Management Features Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O 256-pin MAPBGA Package 225-contact MAPBGA Package
1.2
Target Applications
The i.MXL processor is targeted for advanced information appliances, smart phones, Web browsers, digital MP3 audio players, handheld computers, and messaging applications.
1.3
Ordering Information
Table 1. i.MXL Ordering Information
Package Type 256-lead MAPBGA Frequency 200 MHz Temperature 0OC to 70OC -30 C to 70 C 150 MHz 0OC to 70OC -30 C to 70 C -40OC to 85OC 225-lead MAPBGA 200 MHz 0 C to 70 C -30OC to 70OC 150 MHz 0C to 70C -30OC to 70OC -40 C to 85 C
O O O O O O O O
Table 1 provides ordering information.
Solderball Type Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free
Order Number MC9328MXLVM20(R2) MC9328MXLDVM20(R2) MC9328MXLVM15(R2) MC9328MXLDVM15(R2) MC9328MXLCVM15(R2) MC9328MXLVP20(R2) MC9328MXLDVP20(R2) MC9328MXLVP15(R2) MC9328MXLDVP15(R2) MC9328MXLCVP15(R2)
1.4
* * * * * *
Conventions
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information.
MC9328MXL Technical Data, Rev. 8
This document uses the following conventions:
Freescale Semiconductor
3
Signals and Connections
* *
*
* *
A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. -- Active low signals change from logic level one to logic level zero. -- Active high signals change from logic level zero to logic level one. Negated means that an asserted discrete signal changes logic state. -- Active low signals change from logic level zero to logic level one. -- Active high signals change from logic level one to logic level zero. LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal.
2
Signals and Connections
Table 2. i.MXL Signal Descriptions
Signal Name Function/Notes External Bus/Chip-Select (EIM)
Table 2 identifies and describes the i.MXL processor signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to.
A[24:0] D[31:0] EB0 EB1 EB2 EB3 OE CS [5:0] ECB LBA BCLK (burst clock) RW DTACK
Address bus signals Data bus signals MSB Byte Strobe--Active low external enable byte signal that controls D [31:24]. Byte Strobe--Active low external enable byte signal that controls D [23:16]. Byte Strobe--Active low external enable byte signal that controls D [15:8]. LSB Byte Strobe--Active low external enable byte signal that controls D [7:0]. Memory Output Enable--Active low output enables external data bus. Chip-Select--The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. Active low signal sent by a flash device causing the external burst device to latch the starting burst address. Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal--Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. DTACK signal--The external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed.
MC9328MXL Technical Data, Rev. 8 4 Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name Function/Notes Bootstrap BOOT [3:0] System Boot Mode Select--The operational system boot mode of the i.MXL processor upon system reset is determined by the settings of these pins. SDRAM Controller SDBA [4:0] SDIBA [3:0] MA [11:10] MA [9:0] DQM [3:0] CSD0 CSD1 SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles. SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles. SDRAM address signals SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on SDRAM cycles. SDRAM data enable SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as boot chip-select by properly configuring BOOT [3:0] input pins. SDRAM Row Address Select signal SDRAM Column Address Select signal SDRAM Write Enable signal SDRAM Clock Enable 0 SDRAM Clock Enable 1 SDRAM Clock Not Used Clocks and Resets EXTAL16M XTAL16M EXTAL32K XTAL32K CLKO RESET_IN RESET_OUT POR Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut down. Crystal output 32 kHz crystal input 32 kHz crystal output Clock Out signal selected from internal clock signals. Master Reset--External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset. Reset Out--Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. Power On Reset--Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event.
RAS CAS SDWE SDCKE0 SDCKE1 SDCLK RESET_SF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 5
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name JTAG TRST TDO TDI TCK TMS Test Reset Pin--External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Test Clock to synchronize test logic and control register access through the JTAG port. Test Mode Select to sequence the JTAG test controller's state machine. Sampled on the rising edge of TCK. DMA DMA_REQ BIG_ENDIAN DMA Request--external DMA request signal. Multiplexed with SPI1_SPI_RDY. Big Endian--Input signal that determines the configuration of the external chip-select space. If it is driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven logic-low at reset, the external chip-select space will be configured to little endian. This input must not change state after power-on reset negates or during chip operation. ETM ETMTRACESYNC ETMTRACECLK ETMPIPESTAT [2:0] ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode. Function/Notes
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. CMOS Sensor Interface CSI_D [7:0] CSI_MCLK CSI_VSYNC CSI_HSYNC CSI_PIXCLK Sensor port data Sensor port master clock Sensor port vertical sync Sensor port horizontal sync Sensor port data latch clock LCD Controller LD [15:0] FLM/VSYNC LP/HSYNC LSCLK ACD/OE CONTRAST SPL_SPR PS LCD Data Bus--All LCD signals are driven low after reset and when LCD is off. Frame Sync or Vsync--This signal also serves as the clock signal output for the gate driver (dedicated signal SPS for Sharp panel HR-TFT). Line pulse or H sync Shift clock Alternate crystal direction/output enable. This signal is used to control the LCD bias voltage as contrast control. Program horizontal scan direction (Sharp panel dedicated signal). Control signal output for source driver (Sharp panel dedicated signal).
MC9328MXL Technical Data, Rev. 8 6 Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name CLS REV Function/Notes Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated signal). Signal for common electrode driving signal preparation (Sharp panel dedicated signal). SPI 1 and SPI 2 SPI1_MOSI SPI1_MISO SPI1_SS SPI1_SCLK SPI1_SPI_RDY SPI2_TXD Master Out/Slave In Slave In/Master Out Slave Select (Selectable polarity) Serial Clock Serial Data Ready SPI2 Master TxData Output--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. SPI2 Master RxData Input--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. SPI2 Slave Select--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. SPI2 Serial Clock--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. General Purpose Timers TIN TMR2OUT Timer Input Capture or Timer Input Clock--The signal on this input is applied to both timers simultaneously. Timer 2 Output USB Device USBD_VMO USBD_VPO USBD_VM USBD_VP USBD_SUSPND USBD_RCV USBD_ROE USBD_AFE USB Minus Output USB Plus Output USB Minus Input USB Plus Input USB Suspend Output USB Receive Data USB OE USB Analog Front End Enable Secure Digital Interface SD_CMD SD_CLK SD Command--If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable register, a 4.7K-69K external pull up resistor must be added. MMC Output Clock
SPI2_RXD
SPI2_SS
SPI2_SCLK
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 7
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name SD_DAT [3:0] Function/Notes Data--If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable register, a 50K-69K external pull up resistor must be added. Memory Stick Interface MS_BS MS_SDIO MS_SCLKO MS_SCLKI MS_PI0 MS_PI1 Memory Stick Bus State (Output)--Serial bus control signal Memory Stick Serial Data (Input/Output) Memory Stick Serial Clock (Input)--Serial protocol clock source for SCLK Divider Memory Stick External Clock (Output)--Test clock input pin for SCLK divider. This pin is only for test purposes, not for use in application mode. General purpose Input0--Can be used for Memory Stick Insertion/Extraction detect General purpose Input1--Can be used for Memory Stick Insertion/Extraction detect UARTs - IrDA/Auto-Bauding UART1_RXD UART1_TXD UART1_RTS UART1_CTS UART2_RXD UART2_TXD UART2_RTS UART2_CTS UART2_DSR UART2_RI UART2_DCD UART2_DTR Receive Data Transmit Data Request to Send Clear to Send Receive Data Transmit Data Request to Send Clear to Send Data Set Ready Ring Indicator Data Carrier Detect Data Terminal Ready Serial Audio Port - SSI (configurable to I2S protocol) SSI_TXDAT SSI_RXDAT SSI_TXCLK SSI_RXCLK SSI_TXFS SSI_RXFS Transmit Data Receive Data Transmit Serial Clock Receive Serial Clock Transmit Frame Sync Receive Frame Sync I2C I2C_SCL I2C_SDA I2C Clock I2C Data
MC9328MXL Technical Data, Rev. 8 8 Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name PWM PWMO PWM Output Test Function TRISTATE Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input with a 1 k ohm resistor to ground. (TRI-STATE(R) is a registered trademark of National Semiconductor.) Digital Supply Pins NVDD NVSS Digital Supply for the I/O pins Digital Ground for the I/O pins Supply Pins - Analog Modules AVDD Supply for analog blocks Internal Power Supply QVDD QVSS Power supply pins for silicon internal circuitry Ground pins for silicon internal circuitry Function/Notes
2.1
I/O Pads Power Supply and Signal Multiplexing Scheme
This section describes detailed information about both the power supply for each I/O pin and its function multiplexing scheme. The user can reference information provided in Table 6 on page 18 to configure the power supply scheme for each device in the system (memory and external peripherals). The function multiplexing information also shown in Table 6 allows the user to select the function of each pin by configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions.
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme
I/O Supply Voltage NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 225 BGA Ball D2 C1 D1 E3 E2 E4 E1 F3 256 BGA Ball B1 C2 C1 D2 D1 D3 E2 E3 Primary Signal A24 D31 A23 D30 A22 D29 A21 D28 Dir O I/O O I/O O I/O O I/O 69K 69K ETMPIPE STAT1 O PA29 69K A21 69K ETMPIPE STAT2 O PA30 69K A22 69K ETMTRAC ECLK O PA31 69K A23 PullUp Alternate Signal ETMTRAC ESYNC Dir O GPIO Mux PA0 Pull -Up 69K AIN BIN AOUT Default
SPI2_ SCLK
A24
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 9
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply Voltage NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 225 BGA Ball F1 F4 F2 G3 G2 G4 G1 H4 H2 H3 H1 H5 J1 J3 K1 J4 J2 K4 K2 L4 L1 L3 L2 M1 N1 M2 N2 P1 R1 M3 P2 N3 P3 R2 256 BGA Ball E1 F2 F4 E4 F1 F3 G2 G3 F5 G4 G1 H2 H3 G5 H1 H4 J1 J4 J2 J3 K1 K4 K3 K2 L1 L4 L2 L5 M4 L3 M1 M2 N1 M3 Primary Signal A20 D27 A19 D26 A18 D25 A17 D24 A16 D23 A15 D22 A14 D21 A13 D20 A12 D19 A11 D18 A10 D17 A9 D16 A8 D15 A7 D14 A6 D13 A5 D12 A4 D11 Dir O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K ETMTRAC EPKT0 O PA24 69K A16 69K ETMTRAC EPKT1 O PA25 69K A17 69K ETMTRAC EPKT2 O PA26 69K A18 69K ETMTRAC EPKT3 O PA27 69K A19 PullUp Alternate Signal ETMPIPE STAT0 Dir O GPIO Mux PA28 Pull -Up 69K AIN BIN AOUT Default
A20
MC9328MXL Technical Data, Rev. 8 10 Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply Voltage NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 225 BGA Ball N4 M4 P4 R3 N5 R4 P5 M5 N6 R5 P6 L7 R6 M7 R7 N7 P7 K3 R8 M8 N8 P8 L9 R9 R10 R11 M9 L8 N9 K10 M10 P10 P9 N10 R12 256 BGA Ball P3 N3 P1 N2 P2 R1 T2 R2 R5 T3 R3 T4 N4 R4 N5 P4 P5 T5 M5 T6 T7 R6 P6 N6 R7 P8 R8 P7 N7 N8 M7 T8 M8 R9 P9 Primary Signal EB0 D10 A3 EB1 D9 EB2 A2 EB3 D8 OE A1 CS5 D7 CS4 A0 CS3 D6 CS2 SDCLK CS1 CS0 D5 ECB D4 LBA D3 BCLK D2 PA17 D1 RW MA11 MA10 D0 DQM3 O O I/O O 69K I/O 69K I/O 69K ETMTRAC EPKT4 PA17 69K SPI2_ SS DTACK PA17 Dir O I/O O O I/O O O O I/O O O O I/O O O O I/O O O O O I/O I I/O O I/O 69K ETMTRAC EPKT5 PA18 69K BCLK 69K ETMTRAC EPKT6 PA19 69K LBA 69K ETMTRAC EPKT7 PA20 69K ECB 69K CSD0 CSD0 CSD1 69K PA22 PA21 69K 69K PA22 A0 CSD1 PA23 69K PA23 69K 69K 69K PullUp Alternate Signal Dir GPIO Mux Pull -Up AIN BIN AOUT Default
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 11
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply Voltage NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 AVDD1 QVDD2 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 225 BGA Ball N11 P11 N12 P12 R13 R14 N13 P13 P15 P14 R15 M13 N15 N14 M15 L14 L15 K15 M14 K14 L12 K13 M12 K11 J14 J15 J13 H15 J12 K12 J11 H14 256 BGA Ball T9 N9 R10 M9 L8 T10 R11 P10 N10 T11 T12 R15 P13 T13 T14 T15 R16 P16 M10 N11 R12 M11 P11 N12 R13 P12 R14 N15 L9 N16 P14 P15 Primary Signal DQM2 DQM1 DQM0 RAS CAS SDWE SDCKE0 SDCKE1 RESET_S F CLKO AVDD1 QVDD2 TRST TRISTATE
1
Alternate PullUp Signal Dir
GPIO Mux Pull -Up AIN BIN AOUT Default
Dir O O O O O O O O O O Static Static I I I O I O I O I I I I I I O I I I O I/O
69K
EXTAL16 M XTAL16M EXTAL32 K XTAL32K RESET_I N2 RESET_O UT POR2 BIG_ENDI AN3 BOOT33 BOOT23 BOOT13 BOOT03 TDO4 TMS TCK TDI I2C_SCL I2C_SDA
69K
69K 69K 69K PA16 PA15 69K 69K PA16 PA15
MC9328MXL Technical Data, Rev. 8 12 Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply Voltage NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 225 BGA Ball H13 G14 H12 G13 J10 G15 F15 G12 F14 H11 E14 E15 G11 E13 D14 F13 F12 D15 C14 D13 E12 C13 C12 B15 B14 A15 A14 B13 A13 D12 B12 C11 256 BGA Ball N13 M13 M14 N14 M15 M16 M12 L16 L15 L14 L13 L12 L11 L10 K15 K16 K14 K13 K12 J14 K11 H15 J13 J12 J11 H14 H13 H16 H12 G16 H11 G15 Primary Signal CSI_PIXC LK CSI_HSY NC CSI_VSY NC CSI_D7 CSI_D6 CSI_D5 CSI_D4 CSI_D3 CSI_D2 CSI_D1 CSI_D0 CSI_MCL K PWMO TIN TMR2OUT LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 FLM/VSY NC Dir I I I I I I I I I I I O O I O O O O O O O O O O O O O O O O O O PullUp Alternate Signal Dir GPIO Mux PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 Pull -Up 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K SPI2_ TXD SPI2_ RXD_0 AIN BIN AOUT Default
PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 13
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply Voltage NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD4 225 BGA Ball D11 E11 C10 B11 A12 F10 A11 B10 D10 E10 B9 A10 A9 E8 B8 C9 E9 A8 C8 F9 B7 F8 A7 C7 256 BGA Ball G14 G13 G12 F16 H10 G11 F12 F15 G9 F9 E9 B9 D9 A9 C9 A8 G8 B8 F8 E8 D8 B7 C8 C7 Primary Signal LP/HSYN C ACD/OE CONTRA ST SPL_SPR PS CLS REV LSCLK SPI1_MO SI SPI1_MIS O SPI1_SS SPI1_SCL K SPI1_SPI _RDY UART1_R XD UART1_T XD UART1_R TS UART1_C TS SSI_TXCL K SSI_TXFS SSI_TXDA T SSI_RXD AT SSI_RXCL K SSI_RXFS UART2_R XD Dir O O O O O O O O I/O I/O I/O I/O I/O I O I O I/O I/O O I I I I UART2_D SR UART2_RI UART2_D CD UART2_D TR O O O I PullUp Alternate Signal Dir GPIO Mux PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PB31 Pull -Up 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K
DMA_REQ
AIN
BIN
AOUT
Default
PD13 PD12 PD11 SPI2_ TXD SPI2_ RXD_1 SPI2_ SS SPI2_ SCLK PD10 PD9 PD8 PD7 PD6 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PB31
MC9328MXL Technical Data, Rev. 8 14 Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply Voltage NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 225 BGA Ball D8 E7 F7 B6 C6 A6 D6 A5 B5 A4 B4 A3 C4 D4 B3 A2 C3 A1 B2 B1 256 BGA Ball F7 E7 C6 D7 D6 E6 B6 D5 C5 B5 A5 G7 F6 G6 B4 C4 D4 B3 A3 A2 Primary Signal UART2_T XD UART2_R TS UART2_C TS USBD_VM O USBD_VP O USBD_VM USBD_VP USBD_SU SPND USBD_RC V USBD_RO E USBD_AF E PB19 PB18 PB17 PB16 PB15 PB14 SD_CMD SD_CLK SD_DAT3 Dir O I O O O I I O I/O O O I/O I/O O I I I I/O O I/O MS_BS MS_SCLK O MS_SDIO PB13 PB12 PB11 PullUp Alternate Signal Dir GPIO Mux PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 Pull -Up 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K (pull down) 69K 69K 69K AIN BIN AOUT Default
PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11
NVDD4 NVDD4 NVDD4 NVDD1
C5 D3 C2 D5 G6
E5 B2 C3 K8 A1 H5 T1 H9 H8
SD_DAT2 SD_DAT1 SD_DAT0 NVDD1 NVSS NVDD1 NVSS QVDD1 QVSS
I/O I/O I/O Static Static Static Static Static Static
MS_SCLK I MS_PI1 MS_PI0
PB10 PB9 PB8
PB10 PB9 PB8
NVDD1
E5 H6
QVDD1
J8 E6
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 15
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply Voltage NVDD1 225 BGA Ball F5 J6 NVDD1 G5 K6 NVDD1 J5 H7 NVDD1 K5 J7 NVDD1 L5 G8 NVDD1 L5 H8 K7 NVDD2 H10 G9 QVDD3 F11 G10 NVDD2 C15 H9 QVDD4 D7 L13 NVDD3 D9 J9 K9 NVDD4 NVDD1 NVDD1 NVDD1 NVDD1 G7 F6 L6 M6 K8 L10 L11 M11
1 2
256 BGA Ball J5 K6 K5 M6 H6 J7 L6 J7 L6 K7 J8 L7 T16 K10 J10 J15 J16 K9 J9 A13 B13 A10 A7 A4 A6
Primary Signal NVDD NVSS NVDD1 NVSS NVDD1 NVSS NVDD1 NVSS NVDD1 NVSS NVDD1 NVSS QVSS NVDD2 NVSS QVDD3 QVSS NVDD2 NVSS QVDD4 QVSS NVDD3 NVSS NVSS NVDD4 NVDD1 NVDD1 NVDD1 NVDD1 NVSS NVSS NVSS Dir Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static PullUp
Alternate Signal Dir
GPIO Mux Pull -Up AIN BIN AOUT Default
Pull down this input with 1K resistor to GND. External circuit required to drive this input. 3 Tie this input high (to AVDD) or pull down with 1K resistor to GND. 4 Pull up this output with a resistor to NVDD2.
MC9328MXL Technical Data, Rev. 8 16 Freescale Semiconductor
Electrical Characteristics
3
3.1
Electrical Characteristics
Maximum Ratings
This section contains the electrical specifications and timing diagrams for the i.MXL processor.
Table 4 provides information on maximum ratings which are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on page 18 or the DC Characteristics table.
Table 4. Maximum Ratings
Symbol NVDD QVDD QVDD AVDD BTRFVDD VESD_HBM VESD_MM ILatchup Test Pmax
1
Rating DC I/O Supply Voltage DC Internal (core = 150 MHz) Supply Voltage DC Internal (core = 200 MHz) Supply Voltage DC Analog Supply Voltage DC Bluetooth Supply Voltage ESD immunity with HBM (human body model) ESD immunity with MM (machine model) Latch-up immunity Storage temperature Power Consumption
Minimum -0.3 -0.3 -0.3 -0.3 -0.3 - - - -55 8001
Maximum 3.3 1.9 2.0 3.3 3.3 2000 100 200 150 13002
Unit V V V V V V V mA C mW
A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM(R) core-that is, 7x GPIO, 15x Data bus, and 8x Address bus. 2 A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS application at 200MHz, and where the whole image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.
3.2
Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MXL processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the AVDD pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 17
Electrical Characteristics
Table 5. Recommended Operating Range
Symbol TA Rating Operating temperature range MC9328MXLVM20/MC9328MXLVM15 MC9328MXLVP20/MC9328MXLVP15 Operating temperature range MC9328MXLDVM20/MC9328MXLDVM15 MC9328MXLDVP20/MC9328MXLDVP15 Operating temperature range MC9328MXLCVM15/ MC9328MXLCVP15 I/O supply voltage (if using MSHC, CSI, SPI, LCD, and USBd which are only 3 V interfaces) I/O supply voltage (if not using the peripherals listed above) Internal supply voltage (Core = 150 MHz) Internal supply voltage (Core = 200 MHz) Analog supply voltage Minimum 0 Maximum 70 Unit C
TA
-30
70
C
TA
-40
85
C
NVDD NVDD QVDD QVDD AVDD
2.70 1.70 1.70 1.80 1.70
3.30 3.30 1.90 2.00 3.30
V V V V V
3.3
Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of application note AN2537 on the i.MX applications processor website.
3.4
DC Electrical Characteristics
Table 6. Maximum and Minimum DC Characteristics
Table 6 contains both maximum and minimum DC characteristics of the i.MXL processor.
Number or Symbol Iop
Parameter Full running operating current at 1.8V for QVDD, 3.3V for NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4 decoding playback from external memory card to both external SSI audio decoder and driving TFT display panel, and OS with MMU enabled memory system is running on external SDRAM). Standby current (Core = 150 MHz, QVDD = 1.8V, temp = 25C) Standby current (Core = 150 MHz, QVDD = 1.8V, temp = 55C) Standby current (Core = 150 MHz, QVDD = 2.0V, temp = 25C) Standby current (Core = 150 MHz, QVDD = 2.0V, temp = 55C)
Min -
Typical QVDD at 1.8V = 120mA; NVDD+AVDD at 3.0V = 30mA
Max -
Unit mA
Sidd1 Sidd2 Sidd3 Sidd4
- - - -
25 45 35 60
- - - -
A A A A
MC9328MXL Technical Data, Rev. 8 18 Freescale Semiconductor
Electrical Characteristics
Table 6. Maximum and Minimum DC Characteristics (Continued)
Number or Symbol VIH VIL VOH VOL IIL IIH IOH IOL IOZ Ci Co Input high voltage Input low voltage Output high voltage (IOH = 2.0 mA) Output low voltage (IOL = -2.5 mA) Input low leakage current (VIN = GND, no pull-up or pull-down) Input high leakage current (VIN = VDD, no pull-up or pull-down) Output high current (VOH = 0.8VDD, VDD = 1.8V) Output low current (VOL = 0.4V, VDD = 1.8V) Output leakage current (Vout = VDD, output is high impedance) Input capacitance Output capacitance Parameter Min 0.7VDD - 0.7VDD - - - 4.0 -4.0 - - - Typical - - - - - - - - - - - Max Vdd+0.2 0.4 Vdd 0.4 1 1 - - 5 5 5 Unit V V V V A A mA mA A pF pF
3.5
AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading.
Table 7. Tristate Signal Timing
Pin TRISTATE Parameter Time from TRISTATE activate until I/O becomes Hi-Z Minimum - Maximum 20.8 Unit ns
Table 8. 32k/16M Oscillator Signal Timing
Parameter EXTAL32k input jitter (peak to peak) EXTAL32k startup time EXTAL16M input jitter (peak to peak) 1 EXTAL16M startup time 1
1
Minimum - 800 - TBD
RMS 5 - TBD -
Maximum 20 - TBD -
Unit ns ms - -
The 16 MHz oscillator is not recommended for use in new designs.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 19
Functional Description and Application Information
4
Functional Description and Application Information
This section provides the electrical information including and timing diagrams for the individual modules of the i.MXL.
4.1
Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the ARM920T processor's TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprised of the following: * 32-bit data field * 7-bit address field * A read/write bit The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used in Figure 2.
2a 3a
TRACECLK
1 2b
3b
TRACECLK (Half-Rate Clocking Mode)
Output Trace Port
Valid Data
Valid Data
4a
4b
Figure 2. Trace Port Timing Diagram Table 9. Trace Port Timing Diagram Parameter Table
1.8 0.1 V Ref No. Parameter Minimum 1 2a 2b 3a 3b CLK frequency Clock high time Clock low time Clock rise time Clock fall time 0 1.3 3 - - Maximum 85 - - 4 3 Minimum 0 2 2 - - Maximum 100 - - 3 3 MHz ns ns ns ns 3.0 0.3 V Unit
MC9328MXL Technical Data, Rev. 8 20 Freescale Semiconductor
Functional Description and Application Information
Table 9. Trace Port Timing Diagram Parameter Table (Continued)
1.8 0.1 V Ref No. Parameter Minimum 4a 4b Output hold time Output setup time 2.28 3.42 Maximum - - Minimum 2 3 Maximum - - ns ns 3.0 0.3 V Unit
4.2
DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the pre-divider and Tdck is the output double clock period.
Table 10. DPLL Specifications
Parameter DPLL input clock freq range Pre-divider output clock freq range DPLL output clock freq range Pre-divider factor (PD) Total multiplication factor (MF) MF integer part MF numerator MF denominator Pre-multiplier lock-in time Freq lock-in time after full reset Freq lock-in time after partial reset Phase lock-in time after full reset Phase lock-in time after partial reset Freq jitter (p-p) Phase jitter (p-p) Power supply voltage Power dissipation Vcc = 1.8V Vcc = 1.8V Vcc = 1.8V - Includes both integer and fractional parts - Should be less than the denominator - - FOL mode for non-integer MF (does not include pre-multi lock-in time) FOL mode for non-integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) - Integer MF, FPL mode, Vcc=1.8V - FOL mode, integer MF, fdck = 200 MHz, Vcc = 1.8V Test Conditions Minimum 5 5 80 1 5 5 0 1 - 250 220 300 270 - - 1.7 - Typical - - - - - - - - - 280 (56 s) 250 (50 s) 350 (70 s) 320 (64 s) 0.005 (0.01%) 1.0 (10%) - - Maximum 100 30 220 16 15 15 1022 1023 312.5 300 270 400 370 0.01 1.5 2.5 4 Unit MHz MHz MHz - - - - -
sec
Tref Tref Tref Tref 2*Tdck ns V mW
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 21
Functional Description and Application Information
4.3
Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4. NOTE
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent forward biasing.
90% AVDD
1
POR
10% AVDD
RESET_POR
2
Exact 300ms RESET_DRAM
3
7 cycles @ CLK32
HRESET RESET_OUT
4
14 cycles @ CLK32
CLK32
HCLK
Figure 3. Timing Relationship with POR
5
RESET_IN
14 cycles @ CLK32 HRESET RESET_OUT
4 6
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN
MC9328MXL Technical Data, Rev. 8 22 Freescale Semiconductor
Functional Description and Application Information
Table 11. Reset Module Timing Parameter Table
Ref No. 1 2 3 4 5 6
1
1.8 0.1 V Parameter Min Width of input POWER_ON_RESET Width of internal POWER_ON_RESET (CLK32 at 32 kHz) 7K to 32K-cycle stretcher for SDRAM reset 14K to 32K-cycle stretcher for internal system reset HRESERT and output reset at pin RESET_OUT Width of external hard-reset RESET_IN 4K to 32K-cycle qualifier note1 300 7 14 4 4 Max - 300 7 14 - 4
3.0 0.3 V Unit Min note1 300 7 14 4 4 Max - 300 7 14 - 4 - ms Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 Cycles of CLK32
POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in calculating timing for the start-up process.
4.4
External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the i.MXL processor, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 defines the parameters of signals.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 23
Functional Description and Application Information
(HCLK) Bus Clock
1a 1b
Address Chip-select
2a 2b
3a
3b
Read (Write) OE (rising edge) OE (falling edge) EB (rising edge) EB (falling edge)
6a 5a 4a 4b
4c
4d
5b
5c
5d
LBA (negated falling edge)
6b
LBA (negated rising edge)
6a
6c
7a
7b
BCLK (burst clock) - rising edge BCLK (burst clock) - falling edge
7c
7d
8b
Read Data
9a 8a 9b
Write Data (negated falling)
9a 9c
Write Data (negated rising) DTACK_B
10a 10a
Figure 5. EIM Bus Timing Diagram Table 12. EIM Bus Timing Parameter Table
1.8 0.1 V Ref No. Parameter Min 1a 1b 2a 2b 3a 3b Clock fall to address valid Clock fall to address invalid Clock fall to chip-select valid Clock fall to chip-select invalid Clock fall to Read (Write) Valid Clock fall to Read (Write) Invalid 2.48 1.55 2.69 1.55 1.35 1.86 Typical 3.31 2.48 3.31 2.48 2.79 2.59 Max 9.11 5.69 7.87 6.31 6.52 6.11 Min 2.4 1.5 2.6 1.5 1.3 1.8 Typical 3.2 2.4 3.2 2.4 2.7 2.5 Max 8.8 5.5 7.6 6.1 6.3 5.9 ns ns ns ns ns ns 3.0 0.3 V Unit
MC9328MXL Technical Data, Rev. 8 24 Freescale Semiconductor
Functional Description and Application Information
Table 12. EIM Bus Timing Parameter Table (Continued)
1.8 0.1 V Ref No. Parameter Min 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 7a 7b 7c 7d 8a 8b 9a 9b 9c 10a
1
3.0 0.3 V Unit Max 6.85 6.55 7.04 6.73 5.54 5.24 5.69 5.38 6.73 6.83 6.45 5.64 5.84 5.59 5.80 - - 6.85 5.69 - - Min 2.3 2.1 2.3 2.1 1.9 1.8 1.9 1.7 2.0 1.9 1.9 1.6 1.6 1.5 1.5 5.5 0 1.8 1.4 1.62 2.5 Typical 2.6 2.5 2.6 2.5 2.5 2.4 2.5 2.4 2.7 2.7 2.6 2.6 2.6 2.4 2.5 - - 2.7 2.4 - - Max 6.8 6.5 6.8 6.5 5.5 5.2 5.5 5.2 6.5 6.6 6.4 5.6 5.8 5.4 5.6 - - 6.8 5.5 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Typical 2.62 2.52 2.69 2.59 2.52 2.42 2.59 2.48 2.79 2.79 2.62 2.62 2.62 2.48 2.59 - - 2.72 2.48 - -
Clock1 rise to Output Enable Valid Clock rise to Output Enable Invalid Clock1 fall to Output Enable Valid Clock fall to Output Enable Invalid Clock1 rise to Enable Bytes Valid Clock rise to Enable Bytes Invalid Clock1 fall to Enable Bytes Valid Clock1 fall to Enable Bytes Invalid
1 1 1
2.32 2.11 2.38 2.17 1.91 1.81 1.97 1.76 2.07 1.97 1.91 1.61 1.61 1.55 1.55 5.54 0 1.81 1.45 1.63 2.52
Clock1 fall to Load Burst Address Valid Clock1 fall to Load Burst Address Invalid
Clock1 rise to Load Burst Address Invalid Clock1 rise to Burst Clock rise
Clock1rise to Burst Clock fall Clock1 fall to Burst Clock rise
Clock1 fall to Burst Clock fall Read Data setup time Read Data hold time Clock1 rise to Write Data Valid
Clock1 fall to Write Data Invalid Clock1 rise to Write Data Invalid
DTACK setup time
Clock refers to the system clock signal, HCLK, generated from the System DPLL
4.4.1
DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal function when the external DTACK signal is used for data acknowledgement.
4.4.2
DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in the associated tables.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 25
Functional Description and Application Information
4.4.2.1
WAIT Read Cycle without DMA
3
Address
2
CS5
8
1
EB
programmable min 0ns
9
5
OE
4
WAIT
7
DATABUS XL
6
10
11
Figure 6. WAIT Read Cycle without DMA Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 Characteristic Minimum OE and EB assertion time CS5 pulse width OE negated to address inactive Wait asserted after OE asserted Wait asserted to OE negated Data hold timing after OE negated Data ready after wait asserted OE negated to CS negated OE negated after EB negated Become low after CS5 asserted Wait pulse width See note 2 3T 56.81 - 2T+1.57 T-1.49 0 1.5T-0.68 0.06 0 1T Maximum - - 57.28 1020T 3T+7.33 - T 1.5T-0.06 0.18 1019T 1020T ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXL Technical Data, Rev. 8 26 Freescale Semiconductor
Functional Description and Application Information
4.4.2.2
WAIT Read Cycle DMA Enabled
4
Address
2
CS5
9 10 3 6
1
EB
programmable min 0ns
OE
RW (logic high) WAIT
5 11 7 8 12
L
DATABUS
Figure 7. DTACK WAIT Read Cycle DMA Enabled Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 Characteristic Minimum OE and EB assertion time CS pulse width OE negated before CS5 is negated Address inactived before CS negated Wait asserted after CS5 asserted Wait asserted to OE negated Data hold timing after OE negated Data ready after wait is asserted CS deactive to next CS active OE negate after EB negate Wait becomes low after CS5 asserted See note 2 3T 1.5T-0.68 - - 2T+1.57 T-1.49 - T 0.06 0 Maximum - - 1.5T-0.06 0.05 1020T 3T+7.33 - T - 0.18 1019T ns ns ns ns ns ns ns ns ns ns ns Unit
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 27
Functional Description and Application Information
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
3.0 0.3 V Number 12 Wait pulse width Characteristic Minimum 1T Maximum 1020T ns Unit
Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.3
WAIT Write Cycle without DMA
5
Address
1
CS5
programmable min 0ns
2
3
EB
programmable min 0ns
7 4
10
RW
OE (logic high) WAIT
6 11 9 12 8
DATABUS from i.MXL
Figure 8. WAIT Write Cycle without DMA Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 0.3 V Number 1 2 3 4 5 6 Characteristic Minimum CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated RW negated to Address inactive Wait asserted after CS5 asserted See note 2 See note 2 3T 2.5T-3.63 64.22 - Maximum - - - 2.5T-1.16 - 1020T ns ns ns ns ns ns Unit
MC9328MXL Technical Data, Rev. 8 28 Freescale Semiconductor
Functional Description and Application Information
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
3.0 0.3 V Number 7 8 9 10 11 12 Characteristic Minimum Wait asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted EB negated after CS5 is negated Wait becomes low after CS5 asserted Wait pulse width T+2.66 2T+0.03 - 0.5T 0 1T Maximum 2T+7.96 - T 0.5T+0.5 1019T 1020T ns ns ns ns ns ns Unit
Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register. 3. Address becomes valid and RW asserts at the start of write access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.4
WAIT Write Cycle DMA Enabled
5
Address
1
CS5
programmable min 0ns programmable min 0ns
3
10
2
EB
11
7
RW
4
OE (logic high) WAIT
6 12
9
DATABUS
13
8
Figure 9. WAIT Write Cycle DMA Enabled
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 29
Functional Description and Application Information
Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Characteristic Minimum CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated Address inactived after CS negated Wait asserted after CS5 asserted Wait asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted CS deactive to next CS active EB negate after CS negate Wait becomes low after CS5 asserted Wait pulse width See note 2 See note 2 3T 2.5T-3.63 - - T+2.66 2T+0.03 - T 0.5T 0 1T Maximum - - - 2.5T-1.16 0.09 1020T 2T+7.96 - T - 0.5T+0.5 1019T 1020T ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register. 3. Address becomes valid and RW asserts at the start of write access cycle. 4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.3
EIM External Bus Timing
The External Interface Module (EIM) is the interface to devices external to the i.MXL, including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 defines the parameters of signals.
MC9328MXL Technical Data, Rev. 8 30 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[0] htrans Seq/Nonseq
hwrite
Read
haddr hready weim_hrdata weim_hready
V1
Last Valid Data
V1
BCLK (burst clock) ADDR CS2 R/W Last Valid Address V1
Read
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
V1
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 10. WSC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 31
Functional Description and Application Information
hclk hsel_weim_cs[0] Internal signals - shown only for illustrative purposes htrans hwrite haddr Nonseq
Write
V1
hready
hwdata weim_hrdata
Last Valid Data
Write Data (V1)
Unknown
Last Valid Data
weim_hready
BCLK (burst clock) ADDR CS0 R/W LBA Write Last Valid Address V1
OE
EB
DATA
Last Valid Data
Write Data (V1)
Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8 32 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[0]
htrans hwrite haddr
Nonseq Read V1
hready weim_hrdata Last Valid Data V1 Word
weim_hready
BCLK (burst clock) ADDR CS0 Last Valid Addr Address V1 Address V1 + 2
R/W LBA OE
Read
EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 33
Functional Description and Application Information
hclk
Internal signals - shown only for illustrative purposes
hsel_weim_cs[0] Nonseq
htrans hwrite haddr
Write V1
hready hwdata weim_hrdata Last Valid Data Write Data (V1 Word)
Last Valid Data
weim_hready
BCLK (burst clock) ADDR CS0 Last Valid Addr Address V1 Address V1 + 2
R/W LBA OE
Write
EB
DATA
1/2 Half Word
2/2 Half Word
Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 34 Freescale Semiconductor
Functional Description and Application Information
hclk
Internal signals - shown only for illustrative purposes
hsel_weim_cs[3] htrans hwrite haddr Nonseq
Read V1
hready weim_hrdata
Last Valid Data
V1 Word
weim_hready BCLK (burst clock) ADDR Last Valid Addr CS[3] R/W Read Address V1 Address V1 + 2
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 35
Functional Description and Application Information
hclk hsel_weim_cs[3] htrans hwrite haddr hready hwdata Last Valid Data weim_hrdata Nonseq
Internal signals - shown only for illustrative purposes
Write V1
Write Data (V1 Word)
Last Valid Data
weim_hready
BCLK (burst clock) ADDR Last Valid Addr CS3 R/W LBA OE Write Address V1 Address V1 + 2
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 36 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq Read
hwrite haddr
V1
hready weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock) ADDR CS2 R/W Read Last Valid Addr Address V1 Address V1 + 2
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 37
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq
hwrite haddr
Write V1
hready hwdata Last Valid Data weim_hrdata
Write Data (V1 Word)
Last Valid Data
weim_hready BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2
R/W LBA OE
Write
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 38 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans
Nonseq Read V1
hwrite haddr
hready weim_hrdata Last Valid Data V1 Word
weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V1 + 2
CS2 Read
R/W LBA
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 39
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq Read
hwrite haddr
V1
hready weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock) ADDR CS2 Read Last Valid Addr Address V1 Address V1 + 2
R/W
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 40 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq Write
hwrite haddr
V1
hready Last Valid Data
hwdata weim_hrdata
Write Data (V1 Word)
Unknown
Last Valid Data
weim_hready
BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2
R/W
Write
LBA OE EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 41
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq Write
hwrite haddr
V1
hready hwdata Last Valid Data weim_hrdata
Write Data (V1 Word) Last Valid Data
Unknown
weim_hready
BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2
R/W
Write
LBA
OE EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 42 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] Nonseq Read Nonseq Write
htrans
hwrite haddr
V1
V8
hready
hwdata weim_hrdata
Last Valid Data Last Valid Data
Write Data Read Data
weim_hready
BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V8
CS2
R/W LBA
Read
Write
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
Read Data
DATA
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 43
Functional Description and Application Information
Read hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
Idle
Write
htrans
Nonseq Read
Nonseq Write
hwrite haddr
V1
V8
hready
hwdata
Last Valid Data
Write Data
weim_hrdata
Last Valid Data
Read Data
weim_hready
BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V8
CS2 R/W LBA Read Write
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8 44 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[4]
htrans
Nonseq Write
hwrite haddr
V1
hready hwdata Last Valid Data weim_hrdata
Write Data (Word)
Last Valid Data
weim_hready
BCLK (burst clock) ADDR CS Last Valid Addr Address V1 Address V1 + 2
R/W
Write
LBA OE
EB
DATA
Last Valid Data
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 45
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4]
htrans
Nonseq Read
Nonseq Write
hwrite haddr
V1
V8
hready
hwdata weim_hrdata weim_hready
Last Valid Data Last Valid Data
Write Data Read Data
BCLK (burst clock) ADDR CS4 Last Valid Addr Address V1 Address V8
R/W LBA
Read
Write
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
Read Data
DATA
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8 46 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[4] htrans
Nonseq Read
Idle
Seq Read
hwrite haddr
V1
V2
hready weim_hrdata weim_hready
Last Valid Data
Read Data (V1)
Read Data (V2)
BCLK (burst clock) ADDR
Last Valid
Address V1 CNC
Address V2
CS4 Read
R/W LBA
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
Read Data (V1)
Read Data (V2)
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 47
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4]
htrans
Nonseq Read
Idle
Nonseq Write
hwrite haddr
V1
V8
hready
hwdata weim_hrdata
Last Valid Data Last Valid Data
Write Data Read Data
weim_hready
BCLK (burst clock) ADDR Last Valid Addr Address V1 CNC CS4 R/W LBA OE Address V8
Read
Write
EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8 48 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans hwrite haddr
Nonseq Read V1
Nonse Read V5
Idle
hready
weim_hrdata weim_hready BCLK (burst clock) ADDR
Last Valid Addr
Address V1
Address V5
CS2 Read
R/W LBA
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V5 Word
V6 Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 49
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans hwrite haddr Idle
Nonseq Read V1
Seq Read V2
Seq Read V3
Seq Read V4
hready
weim_hrdata weim_hready BCLK (burst clock)
Last Valid Data
V1 Word
V2 Word
V3 Word
V4 Word
ADDR Last Valid Addr CS2 R/W
Address V1
Read
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V3 Word
V4 Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MC9328MXL Technical Data, Rev. 8 50 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[2] htrans Idle
Nonseq
Seq
hwrite haddr
Read V1
Read V2
hready weim_hrdata Last Valid Data V1 Word V2 Word
weim_hready BCLK (burst clock) ADDR CS2 Read Last Valid Address V1 Address V2
R/W
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
ECB DATA V1 1/2 V1 2/2 V2 1/2 V2 2/2
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 51
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[2] Non seq Read
htrans
Seq
Idle
hwrite haddr
Read
V1
V2
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready BCLK (burst clock) Last
ADDR CS2
Address V1
R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
Read
ECB DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 52 Freescale Semiconductor
Functional Description and Application Information
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[2] htrans Non seq Read V1
Seq
Idle
hwrite haddr
Read V2
hready weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready BCLK (burst clock) ADDR CS2 Last Address V1
R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
Read
ECB DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 53
Functional Description and Application Information
4.4.4
Non-TFT Panel Timing
T1 VSYN T1
T2 HSYN SCLK
T3
XMAX
T4
T2
Ts LD[15:0] Figure 33. Non-TFT Panel Timing Table 17. Non TFT Panel Timing Diagram
Symbol T1 T2 T3 T4
1 2
Parameter HSYN to VSYN delay3 HSYN pulse width VSYN to SCLK SCLK to HSYN
Allowed Register Minimum Value1, 2 0 0 - 0
Actual Value HWAIT2+2 HWIDTH+1 0 T3 Ts5 HWAIT1+1
Unit Tpix4 Tpix - Tpix
Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register. Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong. 3 VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all these 3 signals are active high. 4 Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1). 5 Ts is the shift clock period. Ts = Tpix * (panel data bus width).
4.5
SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The SPI1 Sample Period Control Register (PERIODREG1) and the SPI2 Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI1 Control Register (CONTROLREG1) to match the external SPI master's timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data FIFO. Figure 34 through Figure 38 show the timing relationship of the master SPI using different triggering mechanisms.
MC9328MXL Technical Data, Rev. 8 54 Freescale Semiconductor
Functional Description and Application Information
2 SS 1 SPIRDY
3
5
4
SCLK, MOSI, MISO
Figure 34. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 35. Master SPI Timing Diagram Using SPI_RDY Level Trigger
SS (output)
SCLK, MOSI, MISO
Figure 36. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 37. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
SS (input) 6 SCLK, MOSI, MISO 7
Figure 38. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 55
Functional Description and Application Information
Table 18. Timing Parameter Table for Figure 34 through Figure 38
3.0 0.3 V Ref No. Parameter Minimum 1 2 3 4 5 6 7
1 2
Unit Maximum - - - - - - - ns ns ns ns ns ns ns
SPI_RDY to SS output low SS output low to first SCLK edge Last SCLK edge to SS output high SS output high to SPI_RDY low SS output pulse width SS input low to first SCLK edge SS input pulse width
2T1 3 * Tsclk2 2 * Tsclk 0 Tsclk + WAIT 3 T T
T = CSPI system clock period (PERCLK2). Tsclk = Period of SCLK. 3 WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.
8
SCLK 9 9
Figure 39. SPI SCLK Timing Diagram Table 19. Timing Parameter Table for SPI SCLK
3.0 0.3 V Ref No. Parameter Minimum 8 9 SCLK frequency SCLK pulse width 0 100 Maximum 10 - MHz ns Unit
4.6
LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL Reference Manual.
LSCLK
1
LD[15:0]
Figure 40. SCLK to LD Timing Diagram
MC9328MXL Technical Data, Rev. 8 56 Freescale Semiconductor
Functional Description and Application Information
Table 20. LCDC SCLK Timing Parameter Table
3.0 0.3 V Ref No. 1 Parameter SCLK to LD valid Non-display
T1 T3
Minimum -
Maximum 2 Display region
Unit ns
T4
VSYN HSYN OE LD[15:0]
T2
Line Y
Line 1
Line Y
T5 HSYN SCLK OE LD[15:0] VSYN
T6
XMAX
T7
T8
(1,1) (1,2) (1,X)
T9
T10
Figure 41. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Symbol T1 T2 T3 T4 T5 T6 T7 Description End of OE to beginning of VSYN HSYN period VSYN pulse width End of VSYN to beginning of OE HSYN pulse width End of HSYN to beginning to T9 End of OE to beginning of HSYN Minimum T5+T6 +T7+T9 XMAX+5 T2 2 1 1 1 Corresponding Register Value (VWAIT1*T2)+T5+T6+T7+T9 XMAX+T5+T6+T7+T9+T10 VWIDTH*(T2) VWAIT2*(T2) HWIDTH+1 HWAIT2+1 HWAIT1+1 Unit Ts Ts Ts Ts Ts Ts Ts
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 57
Functional Description and Application Information
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol T8 T9 T9 T10 T10 Note: Description SCLK to valid LD data End of HSYN idle2 to VSYN edge (for non-display region) End of HSYN idle2 to VSYN edge (for Display region) VSYN to OE active (Sharp = 0) when VWAIT2 = 0 VSYN to OE active (Sharp = 1) when VWAIT2 = 0 Minimum -3 2 1 1 2 Corresponding Register Value 3 2 1 1 2 Unit ns Ts Ts Ts Ts
* * * * * *
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns. VSYN, HSYN and OE can be programmed as active high or active low. In Figure 41, all 3 signals are active low. The polarity of SCLK and LD[15:0] can also be programmed. SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 41, SCLK is always active. For T9 non-display region, VSYN is non-active. It is used as an reference. XMAX is defined in pixels.
4.7
Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application (user programming).
3a 3b
Bus Clock
1
2 4b
4a 5a
CMD_DAT Input
Valid Data
5b
Valid Data
7
CMD_DAT Output
Valid Data Valid Data
6a
6b
Figure 42. Chip-Select Read Cycle Timing Diagram
MC9328MXL Technical Data, Rev. 8 58 Freescale Semiconductor
Functional Description and Application Information
Table 22. SDHC Bus Timing Parameter Table
Ref No. 1 2 3a 3b 4a 1.8 0.1 V Parameter Minimum CLK frequency at Data transfer Mode (PP)1--10/30 cards CLK frequency at Identification Mode2 Clock high time --10/30 cards Clock low time1--10/30 cards Clock fall time --10/30 cards Clock rise time1--10/30 cards Input hold time3--10/30 cards Input setup time3--10/30 cards
1 1
3.0 0.3 V Unit Minimum 0 0 10/50 10/50 - Maximum 25/5 400 - - 10/50 MHz kHz ns ns ns
Maximum 25/5 400 - - 10/50 (5.00)3 14/67 (6.67)3 - - - - 16
0 0 6/33 15/75 -
4b
-
-
10/50
ns
5a 5b 6a 6b 7
1 2
10.3/10.3 10.3/10.3 5.7/5.7 5.7/5.7 0
9/9 9/9 5/5 5/5 0
- - - - 14
ns ns ns ns ns
Output hold time3--10/30 cards Output setup time3--10/30 cards
Output delay time3
CL 100 pF / 250 pF (10/30 cards) CL 250 pF (21 cards) 3 C 25 pF (1 card) L
4.7.1
Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card response to the host command starts after exactly NID clock cycles. For the card address assignment, SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and card response is NCR clock cycles as illustrated in Figure 43. The symbols for Figure 43 through Figure 47 are defined in Table 23.
Table 23. State Signal Parameters for Figure 43 through Figure 47
Card Active Symbol Z D * CRC Definition High impedance state Data bits Repetition Cyclic redundancy check bits (7 bits) Symbol S T P E Host Active Definition Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1)
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 59
Functional Description and Application Information
NID cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ
Identification Timing NCR cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ
SET_RCA Timing
Figure 43. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 44, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card. The other two diagrams show the separating periods NRC and NCC.
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** PST Response Content CRC E Z Z Z
Command response timing (data transfer mode)
NRC cycles Response CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
NCC cycles Host Command CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z
Timing of command sequences (all modes)
Figure 44. Timing Diagrams at Data Transfer Mode
Figure 45 shows basic read operation timing. In a read operation, the sequence starts with a single block read command (which specifies the start address in the argument field). The response is sent on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC , beginning from the last bit of the read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command. The data stops two clock cycles after the end bit of the stop command.
MC9328MXL Technical Data, Rev. 8 60 Freescale Semiconductor
Functional Description and Application Information NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z
DAT
Z****Z
Z Z P ****** P S D D D D
*****
NAC cycles
Read Data Timing of single block read
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z
DAT
Z****Z
ZZP
******
P S DDDD
*****
P
*****
P S DDDD
*****
Read Data NAC cycles NAC cycles
Read Data
Timing of multiple block read
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T NST DAT D D D D ***** DDDDE Z Z Z ***** Timing of stop command (CMD12, data transfer mode) Response Content CRC E Z
Valid Read Data
Figure 45. Timing Diagrams at Data Read
Figure 46 shows the basic write operation timing. As with the read operation, after the card response, the data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 61
62
NCR cycles Host Command Response ****** PST Content CRC E Z Z P ****** PP P CMD S T Content CRC E Z Z P DAT Z****Z Z ZZPPS Z ZZPPS Write Data Timing of the block write command NWR cycles CRC status Content Content Z****Z CRC E Z Z S DAT Status ES L*L EZ CRC E Z Z X X X X X X X X X X X X X X X X Z Busy CMD E Z Z P ****** Content CRC E Z Z S EZPPS Status Content CRC E Z Z S Status ES L*L DAT Z Z P P S PPP EZ DAT Z Z P P S Content Write Data CRC status CRC E Z Z X X X X X X X X Z P P S Content Write Data CRC status NWR cycles CRC E Z Z X X X X X X X X X X X X X X X X Z Busy NWR cycles Timing of the multiple block write command
Functional Description and Application Information
Figure 46. Timing Diagrams at Data Write
The stop transmission command may occur when the card is in different states. Figure 47 shows the different scenarios on the bus.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
Freescale Semiconductor
NCR cycles Host Command Card Response ****** PST CRC E Z Z Z Content ST CMD S T Content CRC E Z Z P Host Command Content CRC E DAT D D D D D D D D D D D D D E Z Z S L ****** Write Data Busy (Card is programming) DAT D D D D D D D Z Z S CRC E Z Z S L ****** EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ Stop transmission during data transfer from the host. EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ Stop transmission during CRC status transfer from the card. DAT S L ****** EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ Stop transmission received after last data block. Card becomes busy programming. DAT Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z S L ****** EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ Stop transmission received after last data block. Card becomes busy programming.
Access time delay cycle
Command response cycle
Parameter
Identification response cycle
NID
Symbol
NCR
NAC
Minimum
2
2
5
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)
Table 24. Timing Values for Figure 43 through Figure 47
Figure 47. Stop Transmission During Different Scenarios
MC9328MXL Technical Data, Rev. 8
Maximum
64
5
Functional Description and Application Information
TAAC + NSAC
Unit
Clock cycles
Clock cycles
Clock cycles
63
Functional Description and Application Information
Table 24. Timing Values for Figure 43 through Figure 47 (Continued)
Parameter Command read cycle Command-command cycle Command write cycle Stop transmission cycle Symbol NRC NCC NWR NST Minimum 8 8 2 2 Maximum - - - 2 Unit Clock cycles Clock cycles Clock cycles Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112] NSAC: Data read access time -2 in CLK cycles (NSAC*100) defined in CSD register bit[111:104]
4.7.2
SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data in this mode. The memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (SD_DAT[1] returns to its high level). In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt Period" during the data access, and the controller must sample SD_DAT[1] during this short period to determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes).
CMD
ST
Content
CRC E Z Z P S
Response
EZZZ
******
ZZZ
DAT[1] For 4-bit
Interrupt Period
S
Block Data
E
IRQ
S
Block Data
E
IRQ
LH DAT[1] For 1-bit
Interrupt Period
Figure 48. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the clock running, and allows the user to submit commands as normal. After all commands are submitted, the user can switch back to the data transfer operation and all counter and status values are resumed as access continues.
MC9328MXL Technical Data, Rev. 8 64 Freescale Semiconductor
Functional Description and Application Information
CMD
******
P S T CMD52
CRC E Z Z Z
******
DAT[1] For 4-bit DAT[2] For 4-bit
S
Block Data
EZZL H
S
Block Data
E
S
Block Data
E Z Z L L L L L L L L L L L L L L L L L L L L L HZ S
Block Data
E
Figure 49. SDIO ReadWait Timing Diagram
4.8
Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS, MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in either four-state or two-state access mode. The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1, BS2, and BS3 states are regarded as one packet length and one communication transfer is always completed within one packet length (in four-state access mode). The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 65
Functional Description and Application Information
2
1 4
3
5
MS_SCLKI
6
7
8
MS_SCLKO
11 9 10 11
MS_BS
12 12
MS_SDIO(output)
14
13
MS_SDIO (input) (RED bit = 0)
15 16
MS_SDIO (input) (RED bit = 1)
Figure 50. MSHC Signal Timing Diagram Table 25. MSHC Signal Timing Parameter Table
Ref No. 1 2 3 4 5 6 7 8 9 10 11 MS_SCLKI frequency MS_SCLKI high pulse width MS_SCLKI low pulse width MS_SCLKI rise time MS_SCLKI fall time MS_SCLKO frequency
1
3.0 0.3 V Parameter Minimum - 20 20 - - - 20 15 - - - Maximum 25 - - 3 3 25 - - 5 5 3 MHz ns ns ns ns MHz ns ns ns ns ns Unit
MS_SCLKO high pulse width1 MS_SCLKO low pulse MS_SCLKO rise time1 MS_SCLKO fall time1 width1
MS_BS delay time1
MC9328MXL Technical Data, Rev. 8 66 Freescale Semiconductor
Functional Description and Application Information
Table 25. MSHC Signal Timing Parameter Table (Continued)
Ref No. 12 13 14 15 16
1 2
3.0 0.3 V Parameter Minimum MS_SDIO output delay time1,2 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0) MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1) MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4
4 3
Unit Maximum 3 - - - - ns ns ns ns ns
- 18 0 23 0
Loading capacitor condition is less than or equal to 30pF. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin direction changes. 3 If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge. 4 If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
4.9
Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in Figure 51 and the parameters are listed in Table 26.
2a
System Clock
1 3b
2b 3a 4a
PWM Output
4b
Figure 51. PWM Output Timing Diagram Table 26. PWM Output Timing Parameter Table
1.8 0.1 V Ref No. Parameter Minimum 1 2a 2b 3a System CLK frequency1 Clock high time1 Clock low time
1
3.0 0.3 V Unit Minimum 0 5/10 5/10 - Maximum 100 - - 5/10 MHz ns ns ns
Maximum 87 - - 5
0 3.3 7.5 -
Clock fall time1
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 67
Functional Description and Application Information
Table 26. PWM Output Timing Parameter Table (Continued)
1.8 0.1 V Ref No. Parameter Minimum 3b 4a 4b
1
3.0 0.3 V Unit Minimum - 5 5 Maximum 5/10 - - ns ns ns
Maximum 6.67 - -
Clock rise time1 Output delay time
1
- 5.7 5.7
Output setup time1
CL of PWMO = 30 pF
4.10
SDRAM Controller
This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic random access memory) Controller.
1 SDCLK 2 3S CS 3
3S RAS 3S 3H CAS 3S 3H WE 4S ADDR 4H COL/BA 8 DQ
3H
3H
ROW/BA
5
6 Data 7
3S DQM 3H
Note:
CKE is high during the read/write cycle.
Figure 52. SDRAM Read Cycle Timing Diagram
MC9328MXL Technical Data, Rev. 8 68 Freescale Semiconductor
Functional Description and Application Information
Table 27. SDRAM Read Timing Parameter Table
Ref No. 1 2 3 3S 3H 4S 4H 5 5 5 6 7 7 7 8
1
1.8 0.1 V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM setup time CS, RAS, CAS, WE, DQM hold time Address setup time Address hold time SDRAM access time (CL = 3) SDRAM access time (CL = 2) SDRAM access time (CL = 1) Data out hold time Data out high-impedance time (CL = 3) Data out high-impedance time (CL = 2) Data out high-impedance time (CL = 1) Active to read/write command period (RC = 1) 2.67 6 11.4 3.42 2.28 3.42 2.28 - - - 2.85 - - - tRCD1 Maximum - - - - - - - 6.84 6.84 22 - 6.84 6.84 22 -
3.0 0.3 V Unit Minimum 4 4 10 3 2 3 2 - - - 2.5 - - - tRCD1 Maximum - - - - - - - 6 6 22 - 6 6 22 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 69
Functional Description and Application Information
SDCLK 1 CS 3 2
RAS
6
CAS
WE 4 ADDR / BA
5 7 ROW/BA 8 COL/BA 9 DATA
DQ
DQM
Figure 53. SDRAM Write Cycle Timing Diagram Table 28. SDRAM Write Timing Parameter Table
1.8 0.1 V Ref No. 1 2 3 4 5 6 7 8 9
1 2
3.0 0.3 V Unit Minimum 4 4 10 3 2 tRP2 tRCD2 2 2 Maximum - - - - - - - - - ns ns ns ns ns ns ns ns ns
Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 2.67 6 11.4 3.42 2.28 tRP2 tRCD2 4.0 2.28 Maximum - - - - - - - - -
Active to read/write command delay Data setup time Data hold time
Precharge cycle timing is included in the write timing diagram. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8 70 Freescale Semiconductor
Functional Description and Application Information
SDCLK 1 3 2
CS
RAS
6
CAS 7 7
WE 4 ADDR BA 5 ROW/BA
DQ
DQM
Figure 54. SDRAM Refresh Timing Diagram Table 29. SDRAM Refresh Timing Parameter Table
1.8 0.1 V Ref No. Parameter Minimum 1 2 3 4 5 6 7
1
3.0 0.3 V Unit Minimum 4 4 10 3 2 tRP1 tRC1 Maximum - - - - - - - ns ns ns ns ns ns ns
Maximum - - - - - - -
SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period Auto precharge command period
2.67 6 11.4 3.42 2.28 tRP1 tRC1
tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 71
Functional Description and Application Information
SDCLK
CS
RAS
CAS
WE
ADDR
BA
DQ
DQM
CKE
Figure 55. SDRAM Self-Refresh Cycle Timing Diagram
4.11
USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and how they work from the ground up. Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer.
MC9328MXL Technical Data, Rev. 8 72 Freescale Semiconductor
Functional Description and Application Information
USBD_AFE (Output) 1 USBD_ROE (Output) tPERIOD USBD_VPO (Output) 6 3 tVPO_ROE t ROE_VPO t VMO_ROE 4
USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) USBD_VP (Input) USBD_VM (Input) tROE_VMO 2 tFEOPT 5
Figure 56. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX) Table 30. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX)
Ref No. 1 2 3 4 5 6 3.0 0.3 V Parameter Minimum tROE_VPO; USBD_ROE active to USBD_VPO low tROE_VMO; USBD_ROE active to USBD_VMO high tVPO_ROE; USBD_VPO high to USBD_ROE deactivated tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0) tFEOPT; SE0 interval of EOP tPERIOD; Data transfer rate 83.14 81.55 83.54 248.90 160.00 11.97 Maximum 83.47 81.98 83.80 249.13 175.00 12.03 ns ns ns ns ns Mb/s Unit
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 73
Functional Description and Application Information
USBD_AFE (Output)
USBD_ROE (Output)
USBD_VPO (Output)
USBD_VMO (Output)
USBD_SUSPND (Output)
USBD_RCV (Input) 1
tFEOPR
USBD_VP (Input) USBD_VM (Input)
Figure 57. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX) Table 31. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
3.0 0.3 V Ref No. Parameter Minimum 1 tFEOPR; Receiver SE0 interval of EOP 82 Maximum - ns Unit
4.12
I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA 5 SCL 1 2 6 3
4
Figure 58. Definition of Bus Timing for I2C
MC9328MXL Technical Data, Rev. 8 74 Freescale Semiconductor
Functional Description and Application Information
Table 32. I2C Bus Timing Parameter Table
1.8 0.1 V Ref No. Parameter Minimum 1 2 3 4 5 6 Hold time (repeated) START condition Data hold time Data setup time HIGH period of the SCL clock LOW period of the SCL clock Setup time for STOP condition 182 0 11.4 80 480 182.4 Maximum - 171 - - - - Minimum 160 0 10 120 320 160 Maximum - 150 - - - - ns ns ns ns ns ns 3.0 0.3 V Unit
4.13
Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external clock timing diagrams are shown in Figure 60 through Figure 62. Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.
1
STCK Output
2
STFS (bl) Output
4
6
STFS (wl) Output
8 12 10 11
STXD Output
31
SRXD Input
32
Note: SRXD input in synchronous mode only.
Figure 59. SSI Transmitter Internal Clock Timing Diagram
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 75
Functional Description and Application Information
1
SRCK Output
3
SRFS (bl) Output
5
7
SRFS (wl) Output
9
13 14
SRXD Input
Figure 60. SSI Receiver Internal Clock Timing Diagram
15 16
STCK Input
17
18
STFS (bl) Input
20
22
STFS (wl) Input
24
26
STXD Output
27
28
33
SRXD Input Note: SRXD Input in Synchronous mode only
34
Figure 61. SSI Transmitter External Clock Timing Diagram
MC9328MXL Technical Data, Rev. 8 76 Freescale Semiconductor
Functional Description and Application Information
15 16
SRCK Input
17
19
SRFS (bl) Input
21
23
SRFS (wl) Input
25
29
SRXD Input
30
Figure 62. SSI Receiver External Clock Timing Diagram Table 33. SSI (Port C Primary Function) Timing Parameter Table
1.8 0.1 V Ref No. Parameter Minimum Maximum Minimum Maximum 3.0 0.3 V Unit
Internal Clock Operation1 (Port C Primary Function2) 1 2 3 4 5 6 7 8 9 10 11a 11b 12 13 14 STCK/SRCK clock period1 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 95 1.5 -1.2 2.5 0.1 1.48 -1.1 2.51 0.1 14.25 0.91 0.57 12.88 21.1 0 - 4.5 -1.7 4.3 -0.8 4.45 -1.5 4.33 -0.8 15.73 3.08 3.19 13.57 - - 83.3 1.3 -1.1 2.2 0.1 1.3 -1.1 2.2 0.1 12.5 0.8 0.5 11.3 18.5 0 - 3.9 -1.5 3.8 -0.8 3.9 -1.5 3.8 -0.8 13.8 2.7 2.8 11.9 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low
3 3
STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low
External Clock Operation (Port C Primary Function2) 15 16 17 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period 92.8 27.1 61.1 - - - 81.4 40.7 40.7 - - - ns ns ns
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 77
Functional Description and Application Information
Table 33. SSI (Port C Primary Function) Timing Parameter Table (Continued)
1.8 0.1 V Ref No. Parameter Minimum 18 19 20 21 22 23 24 25 26 27a 27b 28 29 30 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low
3 3
3.0 0.3 V Unit Minimum 0 0 0 0 0 0 0 0 15.8 7.0 8.0 16.2 1.0 0 Maximum 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 24.7 15.9 16.0 25.0 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Maximum 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 28.16 18.13 18.24 28.5 - -
- - - - - - - - 18.01 8.98 9.12 18.47 1.14 0
STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3
3
STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hole time after SRCK low
Synchronous Internal Clock Operation (Port C Primary Function2) 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 15.4 0 - - 13.5 0 - - ns ns
Synchronous External Clock Operation (Port C Primary Function2) 33 34
1
SRXD setup before STCK falling SRXD hold after STCK falling
1.14 0
- -
1.0 0
- -
ns ns
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. 2 There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. 3 bl = bit length; wl = word length.
MC9328MXL Technical Data, Rev. 8 78 Freescale Semiconductor
Functional Description and Application Information
Table 34. SSI (Port B Alternate Function) Timing Parameter Table
Ref No. 1.8 0.1 V Parameter Minimum Maximum Minimum Maximum 3.0 0.3 V Unit
Internal Clock Operation1 (Port B Alternate Function2) 1 2 3 4 5 6 7 8 9 10 11a 11b 12 13 14 STCK/SRCK clock period1 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low 95 1.7 -0.1 3.08 1.25 1.71 -0.1 3.08 1.25 14.93 1.25 2.51 12.43 20 0 - 4.8 1.0 5.24 2.28 4.79 1.0 5.24 2.28 16.19 3.42 3.99 14.59 - - 83.3 1.5 -0.1 2.7 1.1 1.5 -0.1 2.7 1.1 13.1 1.1 2.2 10.9 17.5 0 - 4.2 1.0 4.6 2.0 4.2 1.0 4.6 2.0 14.2 3.0 3.5 12.8 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
External Clock Operation (Port B Alternate Function2) 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3
3
92.8 27.1 61.1 - - - - - - - - 18.9 9.23 10.60
- - - 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 29.07 20.75 21.32
81.4 40.7 40.7 0 0 0 0 0 0 0 0 16.6 8.1 9.3
- - - 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 25.5 18.2 18.7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3
STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 79
Functional Description and Application Information
Table 34. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref No. 28 29 30 1.8 0.1 V Parameter Minimum STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low 17.90 1.14 0 Maximum 29.75 - - Minimum 15.7 1.0 0 Maximum 26.1 - - ns ns ns 3.0 0.3 V Unit
Synchronous Internal Clock Operation (Port B Alternate Function2) 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 18.81 0 - - 16.5 0 - - ns ns
Synchronous External Clock Operation (Port B Alternate Function2) 33 34
1
SRXD setup before STCK falling SRXD hold after STCK falling
1.14 0
- -
1.0 0
- -
ns ns
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. 2 There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. 3 bl = bit length; wl = word length.
4.14
CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing, a control register for statistic data generation, a status register, interface logic, a 32 x 32 image data receive FIFO, and a 16 x 32 statistic data FIFO.
4.14.1
Gated Clock Mode
Figure 63 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge. Figure 64 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in Table 35.
MC9328MXL Technical Data, Rev. 8 80 Freescale Semiconductor
Functional Description and Application Information
1
VSYNC
7
HSYNC
5 2
6
PIXCLK
DATA[7:0]
Valid Data
Valid Data
Valid Data
3
4
Figure 63. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
7
HSYNC
6 2
5
PIXCLK
DATA[7:0]
Valid Data
Valid Data
Valid Data
3
4
Figure 64. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 35. Gated Clock Mode Timing Parameters
Ref No. 1 2 3 4 5 6 7 Parameter csi_vsync to csi_hsync csi_hsync to csi_pixclk csi_d setup time csi_d hold time csi_pixclk high time csi_pixclk low time csi_pixclk frequency Min 180 1 1 1 10.42 10.42 0 Max - - - - - - 48 Unit ns ns ns ns ns ns MHz
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 81
Functional Description and Application Information
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and setup time, according to: Rising-edge latch data max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) In most of case, duty cycle is 50 / 50, therefore max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time)
4.14.2
Non-Gated Clock Mode
Figure 65 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge. Figure 66 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in Table 36.
1
VSYNC
6 4 5
PIXCLK
DATA[7:0]
Valid Data
Valid Data
Valid Data
2
3
Figure 65. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge
MC9328MXL Technical Data, Rev. 8 82 Freescale Semiconductor
Functional Description and Application Information
1
VSYNC
6 5 4
PIXCLK
DATA[7:0]
Valid Data
Valid Data
Valid Data
2
3
Figure 66. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 36. Non-Gated Clock Mode Parameters
Ref No. 1 2 3 4 5 6 Parameter csi_vsync to csi_pixclk csi_d setup time csi_d hold time csi_pixclk high time csi_pixclk low time csi_pixclk frequency Min 180 1 1 10.42 10.42 0 Max - - - - - 48 Unit ns ns ns ns ns MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and setup time, according to: max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) In most of case, duty cycle is 50 / 50, therefore: max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time)
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 83
5
Pin-Out and Package Information
Table 37. i.MXL 256 MAPBGA Pin Assignments
1 2 SD_DAT3 3 SD_CLK 4 NVSS 5 USBD_ AFE USBD_ ROE USBD_ RCV USBD_ SUSPND SD_DAT2 6 NVDD4 7 NVSS SSI_ RXCLK UART2_ RXD USBD_ VMO UART2_ RTS UART2_ TXD PB19 NVSS NVSS NVSS NVSS RW 8 UART1_ RTS SSI_ TXCLK SSI_ RXFS SSI_ RXDAT SSI_ TXDAT SSI_ TXFS UART1_ CTS QVSS NVDD1 NVDD1 CAS MA10 9 UART1_ RXD SPI1_ SCLK UART1_ TXD SPI1_ SPI_RDY SPI1_SS SPI1_ MISO SPI1_ MOSI QVDD1 NVSS NVDD2 TCK RAS 10 NVDD3 11 N.C. 12 N.C. 13 QVDD4 14 N.C. 15 N.C. 16 N.C. A
84 MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor
Pin-Out and Package Information
Table 37 illustrates the package pin assignments for the 256-pin MAPBGA package. For a complete listing of signals, see the Signal Multiplexing Table 3 on page 9.
A
NVSS
B
A24
SD_DAT1
SD_CMD
PB16
USBD_VP UART2_ CTS USBD_ VPO USBD_VM
N.C.
N.C.
N.C.
QVSS
N.C.
N.C. N.C.
N.C.
B
C
A23
D31
SD_DAT0
PB15
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
C
D
A22
D30
D29
PB14
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D
E
A20
A21
D28
D26
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
E
F
A18
D27
D25
A19
A16
PB18
N.C.
N.C.
REV
N.C.
N.C. LP/ HSYNC LD5 LD11 LD14 CSI_D1 CSI_VSYNC
LSCLK FLM/ VSYNC LD9 QVDD3 TMR2OUT CSI_D2 CSI_D6
SPL_SPR
F
G H J K L M
A15 A13 A12 A10 A8 A5
A17 D22 A11 D16 A7 D12
D24 A14 D18 A9 D13 D11
D23 D20 D19 D17 D15 A6
D21 NVDD1 NVDD1 NVDD1 D14 SDCLK
PB17 NVDD1 NVDD1 NVSS NVDD1 NVSS
N.C. PS NVSS NVDD2 TIN RESET_IN RESET_SF1 SDCKE1 DQM0 SDWE 10
CLS LD0 LD6 LD10 PWMO BIG_ ENDIAN RESET_ OUT BOOT3 SDCKE0 CLKO 11
CONTRAST LD2 LD7 LD12 CSI_MCLK CSI_D4
ACD/OE LD4 LD8 LD13 CSI_D0 CSI_ HSYNC CSI_ PIXCLK TRST BOOT1 TRISTATE 13
LD1 LD3 QVSS LD15 CSI_D3 CSI_D5
G H J K L M
N P R T
A4 A3 EB2 NVSS 1
EB1 D9 EB3 A2 2
D10 EB0 A1 OE 3
D7 CS3 CS4 CS5 4
A0 D6 D8 CS2 5
D4 ECB D5 CS1 6
PA17 D2 LBA CS0 7
D1 D3 BCLK2 MA11 8
DQM1 DQM3 D0 DQM2 9
BOOT2 BOOT0 POR AVDD1 12
CSI_D7 I2C_SCL TDO EXTAL16M 14
TMS I2C_SDA QVDD2 XTAL16M 15
TDI XTAL32K EXTAL32K QVSS 16
N P R T
1
This signal is not used and should be floated in an actual application. burst clock
2
Table 38 illustrates the package pin assignments for the 225-contact MAPBGA package. For a complete listing of signals, see the Signal Multiplexing Table 3 on page 9.
Table 38. i.MXL 225 MAPBGA Pin Assignments
1 A SD_CMD 2 PB15 3 PB19 4 USBD_ ROE USBD_ AFE PB18 5 USBD_ SUSPND USBD_ RCV SD_DAT2 6 USBD_VM USBD_ VMO USBD_ VPO USBD_ VP QVSS 7 SSI_ RXFS SSI_ RXDAT UART2_ RXD QVDD4 UART2_ RTS UART2_ CTS NVDD4 NVSS NVSS QVSS CS5 CS4 CS3 D6 A0 7 8 SSI_ TXCLK UART1_ TXD SSI_ TXFS UART2_ TXD UART1_ RXD SSI_ RXCLK NVSS NVSS QVDD1 NVDD1 D2 CS1 CS0 D5 SDCLK 8 9 SPI1_SPI_ RDY SPI1_SS UART1_ RTS NVDD3 UART1_ CTS SSI_ TXDAT NVSS NVSS NVSS NVSS ECB BCLK1 PA17 MA10 D4 9 10 SPI1_ SCLK LSCLK 11 REV SPL_ SPR 12 PS 13 LD2 14 LD4 15 LD5 A
reescale Semiconductor MC9328MXL Technical Data, Rev. 8
1 2
B
SD_DAT3
SD_CLK
PB16
LD0
LD3
LD6
LD7
B
C
D31
SD_DAT0
PB14
CONTRAST FLM/VSYNC SPI1_ MOSI SPI1_ MISO CLS QVSS NVDD2 CSI_D6 D1 NVSS RW D0 MA11 LBA 10
LD8
LD9
LD12
NVDD2
C
D
A23
A24
SD_DAT1
PB17
NVDD1
LP/HSYNC
LD1
LD11
TMR2OUT
LD13 CSI_ MCLK CSI_D4 CSI_D5 TMS BOOT0 XTAL32K EXTAL32K EXTAL16M TRST RESET_SF2 AVDD1 15
D
E
A21
A22
D30
D29
NVDD1
ACD/OE
LD10
TIN
CSI_D0
E
F G H J K L M N P R
A20 A17 A15 A14 A13 A10 D16 A8 D14 A6 1
A19 A18 A16 A12 A11 A9 D15 A7 A5 D11 2
D28 D26 D23 D21 CS2 D17 D13 D12 A4 EB1 3
D27 D25 D24 D20 D19 D18 D10 EB0 A3 EB2 4
NVDD1 NVDD1 D22 NVDD1 NVDD1 NVDD1 EB3 D9 A2 OE 5
NVDD1 NVSS NVSS NVSS NVSS NVDD1 NVDD1 D8 A1 D7 6
QVDD3 PWMO CSI_D1 I2C_SCL BOOT2 NVSS NVSS DQM2 DQM1 D3 11
LD14 CSI_D3 CSI_ VSYNC TCK TDI POR BOOT3 DQM0 RAS DQM3 12
LD15 CSI_D7 CSI_ PIXCLK TDO BIG_ ENDIAN QVSS QVDD2 SDCKE0 SDCKE1 CAS 13
CSI_D2 CSI_HSYNC I2C_SDA BOOT1 RESET_ OUT XTAL16M RESET_IN TRISTATE CLKO SDWE 14
F G H J K L M N P R
Pin-Out and Package Information
Burst Clock This signal is not used and should be floated in an actual application.
85
Pin-Out and Package Information
5.1
MAPBGA 256 Package Dimensions
Figure 67 illustrates the 256 MAPBGA 14 mm x 14 mm x 1.30 mm package, with an 0.8 mm pad pitch. The device designator for the MAPBGA package is VH. Case Outline 1367
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2.INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
Figure 67. i.MXL 256 MAPBGA Mechanical Drawing
MC9328MXL Technical Data, Rev. 8 86 Freescale Semiconductor
Pin-Out and Package Information
5.2
MAPBGA 225 Package Dimensions
Case Outline 1304B
Figure 68 illustrates the 225 MAPBGA 13 mm x 13 mm package.
TOP VIEW
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2.DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. 5.PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE
BOTTOM VIEW
SIDE VIEW
Figure 68. i.MXL 225 MAPBGA Mechanical Drawing
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 87
Product Documentation
6
6.1
Product Documentation
Revision History
Table 39 provides revision history for this release. This history includes technical content revisions only and not stylistic or grammatical changes.
Table 39. i.MXL Data Sheet Revision History Rev. 8
Location Table 2 on page 4 Signal Names and Descriptions Table 3 on page 9 Signal Multiplex Table i.MXL Revision * Added the DMA_REQ signal to table. * Corrected signal name from USBD_OE to USBD_ROE Added Signal Multiplex table from Reference Manual with the following changes: * Changed I/O Supply Voltage,PB31-20, from NVDD3 to NVDD4 * Added 225 BGA column. * Removed 69K pull-up resistor from EB1, EB2, and added to D9 Changed first and second parameters descriptions: From: Reference Clock freq range, To: DPLL input clock freq range From: Double clock freq range, To: DPLL output freq range Added Signal Multiplex table.
Table 10 on page 21
Table 3 on page 9
6.2
Reference Documents
The following documents are required for a complete description of the MC9328MXL and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous i.MX processor products, the following documents are helpful when used in conjunction with this document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029) ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E) MC9328MXL Product Brief (order number MC9328MXLP) MC9328MXL Reference Manual (order number MC9328MXLRM)
The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
MC9328MXL Technical Data, Rev. 8 88 Freescale Semiconductor
NOTES
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 89
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Document Number: MC9328MXL Rev. 8 12/2006

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